Graph Neural Networks (GNNs) have been successfully adopted in many large scale machine learning applications such as computational biology (Zitnik and Leskovec 2017), social networks, creating product listing for shopping sites (Hamilton, Ying, and Leskovec 2017), knowledge graphs (Lin et al. 2015), etc.

The computational requirement of GNNs, however, increases with the input graph size.

This project will look at how we can use custom hardware to accelerate GNN inference. The project will include the following elements:

• Run GNNs on FPGAs, this will include providing an hardware accelerator for GNNs using HLS or SystemVerilog
• Implement floating-point GNN baselines on FPGAs:
  • GCN, GAT, GAT-V2
• Implement and run fixed-point quantized GNNs
• Forward pass uses LUTNet style discretization, backward pass uses Lagrange interpolating method or straight-through estimation method

LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference

GitHub - awai54st/LUTNet

PyG Documentation - pytorch_geometric documentation

This project would be co-supervised with Dr. Erwei Wang from AMD Research.

Meeting Notes (8th Nov)

Timeline